One-Level Storage System

Kilburn, Edwards, Lanigan, Sumner (1961)

Superset of: Dynamic Storage Allocation in the Atlas Computer, Including an Automatic Use of Backing Store, Fotheringham (1961).
What kind of paper?
  • New idea.
  • Motivation.
  • Explanation.
  • Algorithms.
Atlas Architecture
  • Three areas of storage:
  • Private store: For the OS
  • Central store: core and drum
  • Tape store: large persistent memorry
  • ISA
  • Single operand
  • SW-provided (stored in actual CORE memory -- read-only -- think system calls):
  • shift
  • trig functions
  • Device drivers
  • i/O conversion
  • accounting
  • OS
  • Configuration
  • half MIP machine
  • 50 bit words .4 μ sec access time within column
  • Change of column adds 1 μ sec.
  • Working space 1.8 μ sec.
  • Capacity is 10 6 , 96,000 words on 4 drums
  • Up to 8 tape decks, each produces a word every 88 μ sec
  • V-store (registers -- variable store?)
  • b->S
  • s->B
  • B-store
  • Fast core storer (.7 μ sec access)
  • 120 24-bit words
  • main control: execute regular instructions
  • extracode: execute "system calls"
  • interrupt control: handles interrups
  • 24-bit address:
  • block address (9 bits) and line address (9 bits)
  • block is 512 words
  • 0/1 in low bit says that you can access characters in a halfword
  • the second bit indicates which half word
  • 0: most significant half word
  • 1: least significant half word
  • 00: most significant character
  • 11: least significant character
  • 87-bit FP accumulator.
  • 128 24-bit index registers (90 available for general use).
  • Executive store includes ROM for Supervisor.
Memory Arrangement
  • 512-byte blocks/pages.
  • One Page Address Register per in-memory (core) page.
  • PAR contains the address of the page currently resident in memory.
  • Priority scheme of handling tape and drum.
  • Memory is banked into 4 stacks.
Motivation for single-level store
  • Too expensive to make entire memory core store.
  • Too slow to make entire memory drum.
  • Desire: performance of core at cost of drum.
Implementation of single-level store
  • Fully associative lookup on every address .
  • If address found in a PAR, then the data is returned.
  • If no PAR match, generate interrupt.
  • Note placing of address in V-store stores the faulting address.
  • Control is transferred to the equivalent of the page-fault handler.
  • Keep track of drum position in terms of block.
  • Use a WAFL algorithm to assign blocks to drum. .
  • Block address goes in PAR until drum is correctly positioned to prevent transfer to wrong block.
Learning program
  • First use of "use" bits.
  • One use bit per page.
  • Can perform transfers (memory to drum; drum to memory) in either order if you leave room on both media.
  • Lock-out bit prevents programs from accessing blocks that are being transferred.
  • Page replacement: use past to predict future.
  • Periodically read all use bits and store them; reset use bits to 0.
  • Calculate t and T, lengths of the last two intervals of inactivity.
  • Apply following algorithm:
  • If t is > T + 1, use it .
  • Pick page with the maximum T-t such that t != 0 .
  • Pick maximum T .
  • For all blocks on drum, calculate tau which is the time of last use.
  • When moving page from drum to memory, set T to be idle time since last use (current time -tau); t gets set to 0.
Arguments why Atlas provides flexibility
  • Can spread things out in the address space to allow for growth.
  • Programs can move between machines with different memory sizes easily.
  • Only storage allocation a programmer needs to think about is allocating data to pages.