One-Level Storage System
Kilburn, Edwards, Lanigan, Sumner (1961)
Superset of: Dynamic Storage Allocation in the Atlas Computer, Including an Automatic Use of Backing Store, Fotheringham (1961).
What kind of paper?
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New idea.
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Motivation.
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Explanation.
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Algorithms.
Atlas Architecture
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Three areas of storage:
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Private store: For the OS
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Central store: core and drum
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Tape store: large persistent memorry
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ISA
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Single operand
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SW-provided (stored in actual CORE memory -- read-only -- think system calls):
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shift
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trig functions
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Device drivers
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i/O conversion
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accounting
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OS
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Configuration
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half MIP machine
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50 bit words .4
μ
sec access time within column
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Change of column adds 1
μ
sec.
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Working space 1.8
μ
sec.
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Capacity is 10
6
, 96,000 words on 4 drums
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Up to 8 tape decks, each produces a word every 88
μ
sec
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V-store (registers -- variable store?)
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b->S
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s->B
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B-store
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Fast core storer (.7
μ
sec access)
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120 24-bit words
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main control: execute regular instructions
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extracode: execute "system calls"
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interrupt control: handles interrups
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24-bit address:
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block address (9 bits) and line address (9 bits)
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block is 512 words
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0/1 in low bit says that you can access characters in a halfword
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the second bit indicates which half word
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0: most significant half word
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1: least significant half word
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00: most significant character
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11: least significant character
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87-bit FP accumulator.
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128 24-bit index registers (90 available for general use).
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Executive store includes ROM for Supervisor.
Memory Arrangement
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512-byte blocks/pages.
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One Page Address Register per in-memory (core) page.
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PAR contains the address of the page currently resident in memory.
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Priority scheme of handling tape and drum.
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Memory is banked into 4 stacks.
Motivation for single-level store
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Too expensive to make entire memory core store.
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Too slow to make entire memory drum.
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Desire: performance of core at cost of drum.
Implementation of single-level store
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Fully associative lookup on every address .
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If address found in a PAR, then the data is returned.
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If no PAR match, generate interrupt.
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Note placing of address in V-store stores the faulting address.
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Control is transferred to the equivalent of the page-fault handler.
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Keep track of drum position in terms of block.
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Use a WAFL algorithm to assign blocks to drum. .
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Block address goes in PAR until drum is correctly positioned to prevent transfer to wrong block.
Learning program
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First use of "use" bits.
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One use bit per page.
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Can perform transfers (memory to drum; drum to memory) in either order if you leave room on both media.
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Lock-out bit prevents programs from accessing blocks that are being transferred.
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Page replacement: use past to predict future.
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Periodically read all use bits and store them; reset use bits to 0.
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Calculate t and T, lengths of the last two intervals of inactivity.
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Apply following algorithm:
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If t is > T + 1, use it .
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Pick page with the maximum T-t such that t != 0 .
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Pick maximum T .
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For all blocks on drum, calculate tau which is the time of last use.
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When moving page from drum to memory, set T to be idle time since last use (current time -tau); t gets set to 0.
Arguments why Atlas provides flexibility
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Can spread things out in the address space to allow for growth.
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Programs can move between machines with different memory sizes easily.
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Only storage allocation a programmer needs to think about is allocating data to pages.